This invention relates generally to sensors having variable capacitors as sensing elements and more particularly to signal conditioning electronics for providing an improved linear output voltage versus the application of a mechanical stimulus such as pressure or acceleration.
A signal conditioning circuit of this type is shown and described in U.S. Pat. No. 4,982,351, assigned to the assignee of the present invention, the disclosure of which is incorporated herein by this reference. In that patent, a condition responsive element such as a capacitive pressure transducer having a pressure responsive diaphragm for varying transducer capacitance within a selected range in response to variations in pressure forces applied to the diaphragm is shown connected to a reference capacitor in a charge locked loop relation having a common node for forming a capacitance to voltage converter circuit which is ratiometric with respect to supply voltage to vary output voltage within a selected range in response to variation in transducer capacitance in a corresponding range. An array of switches cycles the voltage across the transducer and reference capacitors with opposite transitions with a predetermined frequency so that change in transducer capacitance results in a differential voltage at the common node. That voltage is then amplified to drive a current source-sink network to adjust the sensor output voltage and, by a feedback path, to restore a balanced condition at the node, thereby to maintain the sensor output voltage as a function of the transducer capacitance.
The above circuit has been widely used with various capacitive transducers including pressure and acceleration responsive transducers and provides a nearly linear output voltage. Sensors of this type typically have a total accuracy within a few percent of full scale output voltage. As usage of such sensors increase, higher accuracy as well as lower cost are continuously sought after. Some error in the circuit is related to the feedback circuit which uses a flip-flop latch in which a specified voltage change, positive or negative, is applied to the variable capacitor to offset any error change in the common node. Using this digital approach allows minimization but not elimination of the error charge since it is limited by the incremental charge applied by the digital system. Additionally, a certain amount of non-linearity is found and evidences itself as a parasitic capacitor in parallel with the variable capacitor.